A hardware accelerator is a digital processor that generally operates much faster than a conventional stored program computer. A digital processor normally proceeds through a series of control states in the course of transforming raw data into final data. The states of a process may be designated by the set [P1, P2, . . . Pn]. A set of data transfers are normally associated with each control state. Most data processors, such as most well-known microprocessors, are sequential processors in which only one control state is active at a given time. The sequential processor normally proceeds from control state Pi to Pi+1. If T.sub.p is the time associated with each control state Pi, the total computation time is equal to nT.sub.p (assuming no looping in the process), and the operation rate is 1/(nT.sub.p).
A number of specialized processors have been built in an effort to avoid the limitations of sequential processors. One such specialized type of processor is a pipeline processor. In a pipeline processor, more than one control state is active at any given time, and the data passes through a set of control states that perform operations on the data, much like water flowing through a pipe. The operation of a pipeline processor is illustrated in FIG. 1. The horizontal axis in FIG. 1 represents the control states P1 . . . Pn, and the vertical axis represents time, increasing in the downward direction. In the body of the figure, the symbol 1 represents an active control state, while the symbol 0 designates an inactive control state. At time t1, control state P1 becomes active, and the pipeline starts filling. At time t2, the pipeline is full, and all control states are active. At time t3, the pipeline begins emptying, and the pipeline becomes empty at time t4. The primary advantage of such a system is that after the pipe is full, the operation rate is 1/T.sub.p.
A second specialized form of processor is a parallel processor. When a processor is operating in the parallel mode, all control states Pi can be active at a given moment. However, it is not necessary to "fill" or "empty" all states as in a pipeline configuration. In a parallel processor with n states [P1 . . . Pn], the operation rate is n multiplied by the operation rate of each state. In terms of the discussion above, the operation rate is n*(1/T.sub.p).